View M58WR032EB_856485.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/81 april 2004 m58wr032et M58WR032EB 32 mbit (2mb x 16, multiple bank, burst) 1.8v supply flash memory features summary supply voltage ?v dd = 1.65v to 2.2v for program, erase and read ?v ddq = 1.65v to 3.3v for i/o buffers ?v pp = 12v for fast program (optional) synchronous / asynchronous read ? synchronous burst read mode: 54mhz ? asynchronous/ synchronous page read mode ? random access: 70, 80, 100ns programming time ? 8s by word typical for fast factory program ? double/quadruple word program option ? enhanced factory program options memory blocks ? multiple bank memory array: 4 mbit banks ? parameter blocks (top or bottom location) dual operations ? program erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power up ? any combination of blocks can be locked ?wp for block lock-down security ? 128 bit user programmable otp cells ? 64 bit unique device number ? one parameter block permanently lockable common flash interface (cfi) 100,000 program/erase cycles per block figure 1. package electronic signature ? manufacturer code: 20h ? top device code, m58wr032et: 8814h ? bottom device code, M58WR032EB: 8815h vfbga56 (zb) 7.7 x 9 mm fbga
m58wr032et, M58WR032EB 2/81 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. vfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address inputs (a0-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 write protect (wp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset (rp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 latch enable (l ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 v ssq ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 address latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 command interface - standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/81 m58wr032et, M58WR032EB read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 6. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. security block and protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 command interface - factory program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 bank erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 program phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 quadruple enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 load phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. factory program commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 x-latency bits (cr13-cr11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m58wr032et, M58WR032EB 4/81 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 wrap burst bit (cr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 burst length bits (cr2-cr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6. x-latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 read modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 block locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 reading a block?s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 unlocked state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . 34 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 19. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 10.asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11.asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12.synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5/81 m58wr032et, M58WR032EB figure 13.single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 14.clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 21. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15.write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 22. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16.write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17.reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 18.vfbga56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, bottom view package outline . . . 50 table 25. vfbga56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, package mechanical data . . . . . . 50 figure 19.vfbga56 daisy chain - package connections (top view through package) . . . . . . . . 51 figure 20.vfbga56 daisy chain - pcb connection proposal (top view through package) . . . . . 52 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 26. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 27. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 appendix a.block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 28. top boot block addresses, m58wr032et. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. bottom boot block addresses, M58WR032EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 appendix b.common flash interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 30. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 31. cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 32. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 33. device geometry definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 34. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 35. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 36. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 37. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. bank and erase block region 1 information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 39. bank and erase block region 2 information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 appendix c.flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 21.program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 22.double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 23.quadruple word program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 24.program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . 67 figure 25.block erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 26.erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 27.locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 28.protection register program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 71
m58wr032et, M58WR032EB 6/81 figure 29.enhanced factory program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 enhanced factory program pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 30.quadruple enhanced factory program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 quadruple enhanced factory program pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 appendix d.command interface state tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 40. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 41. command interface states - modify table, next output . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 42. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 43. command interface states - lock table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . 79 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 44. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7/81 m58wr032et, M58WR032EB summary description the m58wr032e is a 32 mbit (2mbit x16) non-vol- atile flash memory that may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.65v to 2.2v v dd supply for the circuitry and a 1.65v to 3.3v v ddq supply for the input/output pins. an optional 12v v pp power supply is provided to speed up custom- er programming. the device features an asymmetrical block archi- tecture. m58wr032e has an array of 71 blocks, and is divided into 4 mbit banks. there are 7 banks each containing 8 main blocks of 32 kwords, and one parameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the multiple bank architecture allows dual operations, while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in table 2. , and the memory maps are shown in figure 4. the param- eter blocks are located at the top of the memory address space for the m58wr032et, and at the bottom for the M58WR032EB. each block can be erased separately. erase can be suspended, in order to perform program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles us ing the supply voltage v dd . there are two enhanced factory programming commands available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst mode, data is output on each cl ock cycle at frequencies of up to 54mhz. the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value i dd4 and the outputs are still driven. the m58wr032e features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection agai nst program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power- up. the device includes a protection register and a security block to increase the protection of a sys- tem?s design. the protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 128 bit segment one-time-programmable (otp) by the user. the user programmable segment can be permanently protected. the security block, pa- rameter block 0, can be permanently protected by the user. figure 5. , shows the security block and protection register memory map. the memory is offered in a vfbga56, 7.7 x 9 mm 0.75 mm ball pitch package and is supplied with all the bits erased (set to ?1?).
m58wr032et, M58WR032EB 8/81 figure 2. logic diagram table 1. signal names ai07303 21 a0-a20 w dq0-dq15 v dd m58wr032et M58WR032EB e v ss 16 g rp wp v ddq v pp l k wait v ssq a0-a20 address inputs dq0-dq15 data input/outputs, command inputs e chip enable g output enable w write enable rp reset wp write protect kclock l latch enable wait wait v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally
9/81 m58wr032et, M58WR032EB figure 3. vfbga connections (top view through package) table 2. bank architecture number bank size parameter blocks main blocks parameter bank 4 mbits 8 blocks of 4 kwords 7 blocks of 32 kwords bank 1 4 mbits - 8 blocks of 32 kwords bank 2 4 mbits - 8 blocks of 32 kwords bank 3 4 mbits - 8 blocks of 32 kwords ---- ---- ---- ---- bank 6 4 mbits - 8 blocks of 32 kwords bank 7 4 mbits - 8 blocks of 32 kwords ai07352 dq1 dq13 dq3 dq12 dq6 dq8 d a1 a3 a6 a9 a12 a15 c a2 a5 a17 a18 a10 b a4 a7 a19 v pp a8 a11 a13 a 8 7 6 5 4 3 2 1 a20 g f e v ss v dd k rp l w a14 wait a16 wp v ddq dq4 dq2 e a0 v ss dq15 dq14 dq11 dq10 dq9 dq0 g dq7 v ssq dq5 v dd v ddq v ssq nc nc
m58wr032et, M58WR032EB 10/81 figure 4. memory map ai07304 m58wr032et - top boot block address lines a20-a0 8 main blocks bank 7 M58WR032EB - bottom boot block address lines a20-a0 32 kword 000000h 007fffh 32 kword 038000h 03ffffh 32 kword 100000h 107fffh 32 kword 138000h 13ffffh 32 kword 140000h 147fffh 32 kword 178000h 17ffffh 32 kword 180000h 187fffh 32 kword 1b8000h 1bffffh 32 kword 1c0000h 1c7fffh 32 kword 1f0000h 1f7fffh 4 kword 1f8000h 1f8fffh 4 kword 1ff000h 1fffffh 8 parameter blocks parameter bank parameter bank 4 kword 000000h 000fffh 4kword 007000h 007fffh 32 kword 008000h 00ffffh 32 kword 038000h 03ffffh 32 kword 040000h 047fffh 32 kword 078000h 07ffffh 32 kword 080000h 087fffh 32 kword 0b8000h 0bffffh 32 kword 0c0000h 0c7fffh 32 kword 0f8000h 0fffffh 32 kword 1c0000h 1c7fffh 32 kword 1f8000h 1fffffh bank 3 bank 2 bank 1 bank 7 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 8 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
11/81 m58wr032et, M58WR032EB signal descriptions see figure 2., logic diagram and table 1., signal names , for a brief overview of the signals connect- ed to this device. address inputs (a0-a20). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the program/erase con- troller. data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a bus write operation. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. output enable (g ). the output enable controls data outputs during the bus read operation of the memory. write enable (w ). the write enable controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. write protect (wp ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock- down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or un- locked. (refer to table 13., lock status ). reset (rp ). the reset input provides a hard- ware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is re- duced to the reset supply current i dd2 . refer to table 18., dc characteristics - currents for the value of i dd2. after reset all blocks are in the locked state and the configuration register is re- set. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic with- out any additional circuitry. it can be tied to v rph (refer to table 19., dc characteristics - voltages ). latch enable (l ). latch enable latches the ad- dress bits on its rising edge. the address latch is transparent when latch e nable is at v il and it is inhibited when latch enable is at v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. clock (k). the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or fallin g, according to the configura- tion settings) when latch enable is at v il . clock is don't care during asynchronous read and in write operations. wait (wait). wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high imped- ance when chip enable is at v ih or reset is at v il . it can be configured to be active during the wait cy- cle or one clock cycle in advance. the wait signal is not gated by output enable. v dd supply voltage . v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. v pp program supply voltage. v pp is both a control input and a power supply pin. the two functions are selected by the voltage range ap- plied to the pin. if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 en- ables these functions (see tables 18 and 19 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable un- til the program/erase algorithm is completed. v ss ground. v ss ground is the reference for the core supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f ce-
m58wr032et, M58WR032EB 12/81 ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors should be as close as possible to the pack- age). see figure 9., ac measurement load cir- cuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents. bus operations there are six standard bus operations that control the device. these are bus read, bus write, ad- dress latch, output disable, standby and reset. see table 3., bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. bus read. bus read operations are used to out- put the contents of the memory array, the elec- tronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figures 10 , 11 , 12 and 13 read ac wave- forms, and tables 20 and 21 read ac character- istics, for details of when the output becomes valid. bus write. bus write operations write com- mands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses can also be latched prior to the write operation by toggling latch enable. in this case the latch enable should be tied to v ih during the bus write operation. see figures 15 and 16 , write ac waveforms, and tables 22 and 23 , write ac characteristics, for details of the timing requirements. address latch. address latch operations input valid addresses. both chip enable and latch en- able must be at v il during address latch opera- tions. the addresses are latched on the rising edge of latch enable. output disable. the outputs are high imped- ance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable and reset are at v ih . the pow- er consumption is reduced to the stand-by level and the outputs are set to high impedance, inde- pendently from the output enable or write enable inputs. if chip enable switches to v ih during a pro- gram or erase operation, the device enters stand- by mode when finished. reset. during reset mode the memory is dese- lected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the standby level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 3. bus operations note: 1. x = don?t care. 2. l can be tied to v ih if the valid address has been previously latched. 3. depends on g . 4. wait signal polarity is configured using the set configuration register command. operation e g w l rp wait (4) dq15-dq0 bus read v il v il v ih v il (2) v ih data output bus write v il v ih v il v il (2) v ih data input address latch v il x v ih v il v ih data output or hi-z (3) output disable v il v ih v ih x v ih hi-z standby v ih xxx v ih hi-z hi-z reset x x x x v il hi-z hi-z
13/81 m58wr032et, M58WR032EB command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will be ignored. refer to table 4., command codes , and appen- dix d. , tables 40 , 41 , 42 and 43 , command inter- face states - modify and lock tables, for a summary of the command interface. the command interface is split into two types of commands: standard commands and factory program commands. the following sections ex- plain in detail how to perform each command. table 4. command codes hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 30h enhanced factory program setup 35h double word program setup 40h program setup 50h clear status register 56h quadruple word program setup 60h block lock setup, block unlock setup, block lock down setup and set configuration register setup 70h read status register 75h quadruple enhanced factory program setup 80h bank erase setup 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block erase confirm, bank erase confirm, block unlock confirm or enhanced factory program confirm ffh read array
m58wr032et, M58WR032EB 14/81 command interface - standard commands the following commands are the basic commands used to read, write to and configure the device. refer to table 5., standard commands , in con- junction with the following text descriptions. read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command and re- turn the addressed bank to read array mode. subsequent read operations will read the ad- dressed location and output the data. a read ar- ray command can be issued in one bank while programming or erasing in another bank. however if a read array command is issued to a bank cur- rently executing a program or erase operation the command will be executed but the output data is not guaranteed. read status register command the status register indicates when a program or erase operation is complete and the success or failure of operation itself. issue a read status register command to read the status register content. the read status register command can be issued at any time, even during program or erase operations. the following read operations output the content of the status register of the addressed bank. the status register is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. see table 8. for the description of the status register bits. this mode supports asynchronous or single synchronous reads only. read electronic signature command the read electronic signature command reads the manufacturer and device codes, the block locking status, the protection register, and the configuration register. the read electronic signature command consists of one write cycle to an address within one of the banks. a subsequent read operation in the same bank will output the manufacturer code, the de- vice code, the protection status of the blocks in the targeted bank, the protection register, or the configuration register (see table 6. ). if a read electronic signature command is issued in a bank that is executing a program or erase op- eration the bank will go into read electronic sig- nature mode, subsequent bus read cycles will output the electronic signature data and the pro- gram/erase controller will continue to program or erase in the background. this mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. read cfi query command the read cfi query command is used to read data from the common flash interface (cfi). the read cfi query command consists of one bus write cycle, to an address within one of the banks. once the command is issued subsequent bus read operations in the same bank read from the common flash interface. if a read cfi query command is issued in a bank that is executing a program or erase operation the bank will go into read cfi query mode, subse- quent bus read cycles will output the cfi data and the program/erase controller will continue to program or erase in the background. this mode supports asynchronous or single synchronous reads only, it does not support page mode or syn- chronous burst reads. the status of the other banks is not affected by the command (see table 11. ). after issuing a read cfi query command, a read array command should be issued to the addressed bank to return the bank to read array mode. see appendix b., common flash inter- face , tables 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 and 39 for details on the information contained in the common flash interface memory area. clear status register command the clear status register command can be used to reset (set to ?0?) error bits sr1, sr3, sr4 and sr5 in the status register. one bus write cycle is required to issue the clear status register com- mand. the clear status register command does not change the read mode of the bank. the error bits in the status register do not auto- matically return to ?0? when a new command is is- sued. the error bits in the status register should be cleared before attempting a new program or erase command. block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. the block erase command can be issued at any moment, re- gardless of whether the block has been pro- grammed or not. two bus write cycles are required to issue the command. the first bus cycle sets up the erase command. the second latches the block address in the program/erase controller and starts it.
15/81 m58wr032et, M58WR032EB if the second bus cycle is not write erase confirm (d0h), status register bits sr4 and sr5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaran- teed when the erase operation is aborted, the block must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register mode un- til a read array, read cfi query or read elec- tronic signature command is issued. during erase operations the bank containing the block being erased will only accept the read ar- ray, read status register, read electronic signa- ture, read cfi query and the program/erase suspend command, all other commands will be ig- nored. refer to dual operations section for de- tailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 14., program, erase times and program, erase endurance cycles . see appendix c. , figure 25., block erase flow- chart and pseudo code , for a suggested flowchart for using the block erase command. program command the memory array can be programmed word-by- word. only one word in one bank can be pro- grammed at any one time. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and the data to be written and starts the program/erase controller. after programming has started, read operations in the bank being programmed output the status register content. during program operations the bank being pro- grammed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend com- mand. refer to dual operations section for de- tailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 14., program, erase times and program, erase endurance cy- cles . programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. see appendix c. , figure 21., program flow- chart and pseudo code , for the flowchart for using the program command. program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. a bank erase operation cannot be suspended. one bus write cycle is required to issue the pro- gram/erase command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of the status register will be set to ?1?. the com- mand can be addressed to any bank. during program/erase suspend the command in- terface will accept the program/erase resume, read array (cannot read the erase-suspended block or the program-suspended word), read status register, read electronic signature and read cfi query commands. additionally, if the suspend operation was erase then the clear sta- tus register, program, block lock, block lock- down or block unlock commands will also be ac- cepted. the block being erased may be protected by issuing the block lock, block lock-down or protection register program commands. only the blocks not bei ng erased may be read or pro- grammed correctly. when the program/erase re- sume command is issued the operation will complete. refer to the dual operations section for detailed information about simultaneous opera- tions allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c. , figure 24., program suspend & resume flowchart and pseudo code , and fig- ure 26., erase suspend & resume flowchart and pseudo code , for flowcharts for using the pro- gram/erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend command has paused it. one bus write cycle is required to issue the command. the command can be written to any address. the program/erase resume command does not change the read mode of the banks. if the sus- pended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corre- sponding data. if the bank was in read array mode subsequent read oper ations will output in- valid data. if a program command is issued during a block erase suspend, then the erase cannot be re- sumed until the programming operation has com- pleted. it is possible to accumulate suspend operations. for example: suspend an erase oper- ation, start a programming operation, suspend the
m58wr032et, M58WR032EB 16/81 programming operation then read the array. see appendix c. , figure 24., program suspend & resume flowchart and pseudo code , and figure 26., erase suspend & resume flowchart and pseudo code , for flowcharts for using the pro- gram/erase resume command. protection register program command the protection register program command is used to program the 128 bit user one-time-pro- grammable (otp) segment of the protection reg- ister and the protection register lock. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two write cycles are required to issue the protec- tion register program command. the first bus cycle sets up the protection register program command. the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the segment can be protected by programming bit 1 of the protection lock register. bit 1 of the pro- tection lock register also protects bit 2 of the pro- tection lock register. programming bit 2 of the protection lock register will result in a permanent protection of parameter block #0 (see figure 5., security block and protection register memory map ). attempting to program a previously protect- ed protection register will result in a status reg- ister error. the protection of the protection register and/or the security block is not revers- ible. the protection register program cannot be sus- pended. see appendix c. , figure 28., protec- tion register program flowchart and pseudo code , for a flowchart for using the protection reg- ister program command. set configuration register command the set configuration register command is used to write a new value to the configuration register which defines the burst length, type, x latency, synchronous/asynchronous read mode and the valid clock edge configuration. two bus write cycles are required to issue the set configuration register command. the first cycle writes the setup command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. the banks remain in read mode when the set configuration register command is issued. the value for the configuration register is always presented on a0-a15. cr0 is on a0, cr1 on a1, etc.; the other address bits are ignored. block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table 13. shows the lock status after issuing a block lock command. the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a block unlock command. refer to the section, block locking, for a detailed explanation. see appendix c. , figure 27., locking operations flowchart and pseudo code , for a flowchart for using the lock command. block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to is- sue the block unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table 13. shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and ap- pendix c. , figure 27., locking operations flow- chart and pseudo code , for a flowchart for using the unlock command. block lock-down command a locked or unlocked block can be locked-down by issuing the block lock-down command. a locked- down block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock com- mand. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock command.
17/81 m58wr032et, M58WR032EB the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table 13. shows the lock status af- ter issuing a block lock-down command. refer to the section, block locking, for a detailed explana- tion and appendix c. , figure 27., locking oper- ations flowchart and pseudo code , for a flowchart for using the lock-down command. table 5. standard commands note: 1. x = don?t care, wa=word address in targeted bank, rd=read data, srd=status register data, esd=electronic signature data, qd=query data, ba=block address, bka= bank address, pd=program data, pra=protection register address, prd=protection register data, crd=configuration register data. 2. must be same bank as in the first cycle. the signature addresses are listed in table 6. 3. any address within the bank can be used. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write bka 50h block erase 2 write bka or ba (3) 20h write ba d0h program 2 write bka or wa (3) 40h or 10h write wa pd program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka or ba (3) 60h write ba 01h block unlock 2 write bka or ba (3) 60h write ba d0h block lock-down 2 write bka or ba (3) 60h write ba 2fh
m58wr032et, M58WR032EB 18/81 table 6. electronic signature codes note: cr=configuration register. figure 5. security block and protection register memory map code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 8814 bottom bank address + 01 8815 block protection locked block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 reserved bank address + 03 reserved configuration register bank address + 05 cr protection register lock st factory default bank address + 80 0006 security block permanently locked 0002 otp area permanently locked 0004 security block and otp area permanently locked 0000 protection register bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 8c otp area ai06181 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 8ch 85h 84h 81h 80h protection register security block
19/81 m58wr032et, M58WR032EB command interface - factory program commands the factory program commands are used to speed up programming. they require v pp to be at v pph except for the bank erase command which also operates at v pp = v dd . refer to table 7., fac- tory program commands , in conjunction with the following text descriptions. the use of the factory program commands re- quire certain operating conditions: v pp must be set to v pph (except for bank erase command) v dd must be within operating range ambient temperature, t a must be 25c 5c the targeted block must be unlocked refer to table 7., factory program commands , in conjunction with the following text descriptions. bank erase command the bank erase command can be used to erase a bank. it sets all the bits within the selected bank to ?1?. all previous data in the bank is lost. the bank erase command will ignore any protected blocks within the bank. if all blocks in the bank are pro- tected then the bank erase operation will abort and the data in the bank will not be changed. the status register will not output any error. bank erase operations can be performed at both v pp = v pph and v pp = v dd . two bus write cycles are required to issue the command. the first bus cycle sets up the bank erase command. the second latches the bank address in the program/erase controller and starts it. if the second bus cycle is not write bank erase confirm (d0h), status register bits sr4 and sr5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the bank must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register mode un- til a read array, read cfi query or read elec- tronic signature command is issued. during bank erase operations the bank being erased will only accept the read array, read sta- tus register, read electronic signature and read cfi query command, all other commands will be ignored. for optimum performance, bank erase com- mands should be limited to a maximum of 100 pro- gram/erase cycles per block. after 100 program/ erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. dual operations are not supported during bank erase operations and the command cannot be suspended. typical erase times are given in table 14., pro- gram, erase times and program, erase endur- ance cycles . double word program command the double word program command improves the programming throughput by writing a page of two adjacent words in parallel. the two words must differ only for the address a0. three bus write cycles are necessary to issue the double word program command. the first bus cycle sets up the double word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations in the bank being programmed output the status register content after the pro- gramming has started. during double word program operations the bank being programmed will only accept the read ar- ray, read status register, read electronic signa- ture and read cfi query command, all other commands will be ignored. dual operations are not supported during double word program oper- ations and the command cannot be suspended. typical program times are given in table 14., pro- gram, erase times and program, erase endur- ance cycles . programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. see appendix c. , figure 22., double word pro- gram flowchart and pseudo code , for the flow- chart for using the double word program command. quadruple word program command the quadruple word program command im- proves the programming throughput by writing a page of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. five bus write cycles are necessary to issue the quadruple word program command. the first bus cycle sets up the double word program command.
m58wr032et, M58WR032EB 20/81 the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written. the fourth bus cycle latches the address and the data of the third word to be written. the fifth bus cycle latc hes the address and the data of the fourth word to be written and starts the program/erase controller. read operations to the bank being programmed output the status register content after the pro- gramming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. during quadruple word program operations the bank being programmed will only accept the read array, read status register, read electronic sig- nature and read cfi query command, all other commands will be ignored. dual operations are not supported during quadru- ple word program operations and the command cannot be suspended. typical program times are given in table 14., program, erase times and program, erase endurance cycles . see appendix c. , figure 23., quadruple word program flowchart and pseudo code , for the flowchart for using the quadruple word program command. enhanced factory program command the enhanced factory program command can be used to program large streams of data within any one block. it greatly reduces the total program- ming time when a large number of words are writ- ten to a block at any one time. dual operations are not supported during the en- hanced factory program operation and the com- mand cannot be suspended. for optimum performance the enhanced factory program commands should be limited to a maxi- mum of 10 program/erase cycles per block. if this limit is exceeded the internal algorithm will contin- ue to work properly but some degradation in per- formance is possible. typical program times are given in table 14. the enhanced factory program command has four phases: the setup phase, the program phase to program the data to the memory, the verify phase to check that the data has been correctly programmed and reprogram if necessary and the exit phase. refer to table 7., factory program commands , and figure 29., enhanced factory program flowchart . setup phase. the enhanced factory program command requires two bus write operations to ini- tiate the command. the first bus cycle sets up the enhanced factory program command. the second bus cycle confirms the command. the status register p/e.c. bit sr7 should be read to check that the p/e.c. is ready. after the confirm command is issued, read operations output the status register data. the read status register command must not be issued as it will be interpreted as data to program. program phase. the program phase requires n+1 cycles, where n is the number of words (refer to table 7., factory program commands and fig- ure 29., enhanced factory program flowchart ). three successive steps are required to issue and execute the program phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address can either remain the start address, in which case the p/e.c. increments the address location or the address can be incremented in which case the p/e.c. jumps to the new address. if any address that is not in the same block as the start address is given with data ffffh, the program phase terminates and the verify phase begins. the status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. finally, after all words have been pro- grammed, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the programming phase. if the data is not ffffh, the command is ignored. the memory is now set to enter the verify phase. verify phase. the verify phase is similar to the program phase in that all words must be resent to the memory for them to be checked against the programmed data. the program/erase controller checks the stream of data with the data that was programmed in the program phase and repro- grams the memory location if necessary. three successive steps are required to execute the verify phase of the command. 1. use one bus write operation to latch the start address and the first word, to be verified. the status register bit sr0 should be read to
21/81 m58wr032et, M58WR032EB check that the program/erase controller is ready for the next word. 2. each subsequent word to be verified is latched with a new bus write operation. the words must be written in the same order as in the program phase. the address can remain the start address or be incremented. if any address that is not in the same block as the start address is given with data ffffh, the verify phase terminates. status register bit sr0 should be read to check that the p/e.c. is ready for the next word. 3. finally, after all words have been verified, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the verify phase. if the verify phase is successfully completed the memory remains in read status register mode. if the program/erase controller fails to reprogram a given location, the error w ill be signaled in the sta- tus register. exit phase. status register p/e.c. bit sr7 set to ?1? indicates that the device has returned to read mode. a full status register check should be done to ensure that the block has been successfully pro- grammed. see the section on the status register for more details. quadruple enhanced factory program command the quadruple enhanced factory program com- mand can be used to program one or more pages of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. dual operations are not supported during quadru- ple enhanced factory program operations and the command cannot be suspended. the quadruple enhanced factory program com- mand has four phases: the setup phase, the load phase where the data is loaded into the buffer, the combined program and verify phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the exit phase. unlike the en- hanced factory program it is not necessary to re- submit the data for the verify phase. the load phase and the program and verify phase can be repeated to program any number of pages within the block. setup phase. the quadruple enhanced factory program command requires one bus write opera- tion to initiate the load phase. after the setup command is issued, read operations output the status register data. the read status register command must not be issued as it will be interpreted as data to program. load phase. the load phase requires 4 cycles to load the data (refer to table 7., factory program commands and figure 30., quadruple enhanced factory program flowchart ). once the first word of each page is written it is impossible to exit the load phase until all four words have been written. two successive steps are required to issue and execute the load phase of the quadruple en- hanced factory program command. 1. use one bus write operation to latch the start address and the first word of the first page to be programmed. for subsequent pages the first word address can remain the start address (in which case the next page is programmed) or can be any address in the same block. if any address with data ffffh is given that is not in the same block as the start address, the device enters the exit phase. for the first load phase status register bit sr7 should be read after the first word has been issued to check that the command has been accepted (bit 7 set to ?0?). this check is not required for subsequent load phases. 2. each subsequent word to be programmed is latched with a new bus write operation. the address is only checked for the first word of each page as the order of the words to be programmed is fixed. the memory is now set to enter the program and verify phase. program and verify phase. in the program and verify phase the four words that were loaded in the load phase are programmed in the memory array and then verified by the program/erase con- troller. if any errors are found the program/erase controller reprograms the location. during this phase the status register shows that the pro- gram/erase controller is busy, status register bit sr7 set to ?0?, and that the device is not waiting for new data, status register bit sr0 set to ?1?. when status register bit sr0 is set to ?0? the program and verify phase has terminated. once the verify phase has successfully complet- ed subsequent pages in the same block can be loaded and programmed. the device returns to the beginning of the load phase by issuing one bus write operation to latch the address and the first of the four new words to be programmed. exit phase. finally, after all the pages have been programmed, write one bus write operation with data ffffh to any address outside the block con- taining the start address, to terminate the load and program and verify phases. a full status register check should be done to en- sure that the block has been successfully pro- grammed. see the section on the status register for more details.
m58wr032et, M58WR032EB 22/81 if the program and verify phase has successfully completed the memory returns to read mode. if the p/e.c. fails to program and reprogram a given location, the error will be signaled in the status register. table 7. factory program commands note: 1. wa=word address in targeted bank, bka= bank address, pd=program data, ba=block address. 2. wa1 is the start address. not wa1 is any address that is not in the same block as wa1. 3. address can remain starting address wa1 or be incremented. 4. word addresses 1 and 2 must be consecutive addresses differing only for a0. 5. word addresses 1,2,3 and 4 must be consecutive addresses differing only for a0 and a1. 6. a bus read must be done between each write cycle where the data is programmed or verified to read the status register and check that the memory is ready to accept the next data. n = number of words, i = number of pages to be programmed. 7. address is only checked for the first word of each page as the order to program the words in each page is fixed so subsequent words in each page can be written to any address. 8. any address within the bank can be used. 9. any address within the block can be used. command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data bank erase 2 bka 80h bka d0h double word program (4) 3 bka or wa1 (8) 35h wa1 pd1 wa2 pd2 quadruple word program (5) 5 bka or wa1 (8) 56h wa1 pd1 wa2 pd2 wa3 pd3 wa4 pd4 enhanced factory program (6) setup, program 2+n +1 bka or wa1 (8) 30h ba or wa1 (9) d0h wa1 (2) pd1 wan (3) pa n not wa1 (2) ffffh verify, exit n+1 wa1 (2) pd1 wa2 (3) pd2 wa3 (3) pd3 wan (3) pa n not wa1 (2) ffffh quadruple enhanced factory program (5,6) setup, first load 5 bka or wa1 (8) 75h wa1 (2) pd1 wa2 (7) pd2 wa3 (7) pd3 wa4 (7) pd4 first program & verify automatic subsequent loads 4 wa1i (2) pd1i wa2i (7) pd2i wa3i (7) pd3i wa4i (7) pd4i subsequent program & verify automatic exit 1 not wa1 (2) ffffh
23/81 m58wr032et, M58WR032EB status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register, refer to read status register command section for more de- tails. to output the contents, the status register is latched and updated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank, always read the status register during pro- gram and erase operations. the various bits convey information about the sta- tus and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on er- rors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. sr7 to sr1 refer to the status of the device while sr0 refers to the status of the ad- dressed bank. the bits in the status register are summarized in table 8., status register bits . refer to table 8. in conjunction with the following text descriptions. program/erase controller status bit (sr7). the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the pro- gram/erase controller is active; when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block lock status bits should be tested for errors. erase suspend status bit (sr6). the erase suspend status bit indicates that an erase opera- tion has been suspended or is going to be sus- pended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/ erase suspend command has been issued and the memory is waiting for a program/erase re- sume command. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). sr7 is set within the erase suspend latency time of the program/erase suspend command being issued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status bit (sr5). the erase status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. when the erase status bit is high (set to ?1?), the program/erase controller has applied the maxi- mum number of pulses to the block or bank and still failed to verify that it has erased correctly. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status bit (sr4). the program status bit is used to identify either a program failure or an attempt to program a ?1? to an already pro- grammed bit when v pp = v pph . when the pro- gram status bit is high (set to ?1?), the program/ erase controller has applied the maximum num- ber of pulses to the byte and still failed to verify that it has programmed correctly. after an attempt to program a ?1? to an already pro- grammed bit, the program status bit sr4 goes high (set to ?1?) only if v pp = v pph . if v pp is differ- ent from v pph , sr4 remains low (set to ?0?) and the attempt is not shown. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inac- tive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v pp status bit (sr3). the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program
m58wr032et, M58WR032EB 24/81 or erase operation. indeterminate results can oc- cur if v pp becomes invalid during an operation. when the v pp status bit is low (set to ?0?), the volt- age on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and pro- gram and erase operations cannot be performed. once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status bit (sr2). the pro- gram suspend status bit indicates that a program operation has been suspended in the addressed block. when the program suspend status bit is high (set to ?1?), a program/erase suspend com- mand has been issued and the memory is waiting for a program/erase resume command. the pro- gram suspend status should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). sr2 is set within the program suspend latency time of the program/erase suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status bit (sr1). the block protection status bit can be used to identify if a program or block erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to ?1?), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. bank write/multiple word program status bit (sr0). the bank write status bit indicates wheth- er the addressed bank is programming or erasing. in enhanced factory program mode the multiple word program bit shows if a word has finished programming or verifying depending on the phase. the bank write status bit should only be consid- ered valid when the program/erase controller sta- tus sr7 is low (set to ?0?). when both the program/erase controller status bit and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase con- troller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in enhanced factory program mode if multiple word program status bit is low (set to ?0?), the de- vice is ready for the next word, if the multiple word program status bit is high (set to ?1?) the device is not ready for the next word. note: refer to appendix c., flowcharts and pseudo codes , for using the status reg- ister.
25/81 m58wr032et, M58WR032EB table 8. status register bits note: logic level ?1? is high, ?0? is low. bit name type logic level definition sr7 p/e.c. status status ?1? ready ?0? busy sr6 erase suspend status status ?1? erase suspended ?0? erase in progress or completed sr5 erase status error ?1? erase error ?0? erase success sr4 program status error ?1? program error ?0? program success sr3 v pp status error ?1? v pp invalid, abort ?0? v pp ok sr2 program suspend status status ?1? program suspended ?0? program in progress or completed sr1 block protection status error ?1? program/erase on protected block, abort ?0? no operation to protected blocks sr0 bank write status status ?0? sr7 = ?0? program or erase operation in addressed bank sr7 = ?1? no program or erase operation in the device '1' sr7 = ?0? program or erase operation in a bank other than the addressed bank sr7 = ?1? not allowed multiple word program status (enhanced factory program mode) status '1' sr7 = ?0? the device is not ready for the next word sr7 = ?1? not allowed '0' sr7 = ?0? the device is ready for the next word sr7 = ?1? the device is exiting from efp
m58wr032et, M58WR032EB 26/81 configuration register the configuration register is used to configure the type of bus access that the memory will per- form. refer to read modes section for details on read operations. the configuration register is set through the command interface. after a reset or power-up the device is configured for asynchronous page read (cr15 = 1). the configuration register bits are described in table 9. they specify the selec- tion of the burst length, burst type, burst x latency and the read operation. refer to figures 6 and 7 for examples of synchronous burst configurations. read select bit (cr15) the read select bit, cr15, is used to switch be- tween asynchronous and synchronous bus read operations. when the read select bit is set to ?1?, read operations are asynchronous; when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is support- ed in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to?1? for asynchronous access. x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in ta- ble 9., configuration register . the correspondence between x-latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. two conditions must be satisfied: 1. depending on whether t avk_cpu or t delay is supplied either one of the following two equations must be satisfied: (n + 1) t k t acc - t avk_cpu + t qvk_cpu (n + 2) t k t acc + t delay + t qvk_cpu 2. and also t k > t kqv + t qvk_cpu where n is the chosen x-latency configuration code t k is the clock period t avk_cpu is clock to address valid, l low, or e low, whichever occurs last t delay is address valid, l low, or e low to clock, whichever occurs last t qvk_cpu is the data setup time required by the system cpu, t kqv is the clock to data valid time t acc is the random access time of the device. refer to figure 6., x-latency and data output configuration example . wait polarity bit (cr10) in synchronous burst mode the wait signal indi- cates whether the output data are valid or a wait state must be inserted. the wait polarity bit is used to set the polarity of the wait signal. when the wait polarity bit is set to ?0? the wait signal is active low. when the wait polarity bit is set to ?1? the wait signal is active high (default). data output configuration bit (cr9) the data output configuration bit determines whether the output remains valid for one or two clock cycles. when the data output configuration bit is ?0? the output data is valid for one clock cycle, when the data output configuration bit is ?1? the output data is valid for two clock cycles. the data output configuration depends on the condition: t k > t kqv + t qvk_cpu where t k is the clock period, t qvk_cpu is the data setup time required by the system cpu and t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to ?1? (two clock cycles). refer to figure 6., x-latency and data output configuration exam- ple . wait configuration bit (cr8) in burst mode the wait bit controls the timing of the wait output pin, wait. when wait is asserted, data is not valid and when wait is deasserted, data is valid. when the wait bit is ?0? the wait out- put pin is asserted during the wait state. when the wait bit is ?1? (default) the wait output pin is assert- ed one clock cycle before the wait state. burst type bit (cr7) the burst type bit is used to configure the se- quence of addresses read as sequential or inter- leaved. when the burst type bit is ?0? the memory outputs from interleaved addresses; when the burst type bit is ?1? (default) the memory outputs from sequential addresses. see table 10., burst type definition , for the sequence of addresses output from a given starting address in each mode. valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to config- ure the active edge of the clock, k, during syn- chronous burst read operations. when the valid clock edge bit is ?0? the falling edge of the clock is the active edge; when the valid clock edge bit is ?1? the rising edge of the clock is active. wrap burst bit (cr3) the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary
27/81 m58wr032et, M58WR032EB (no wrap). the wrap burst bit is used to select be- tween wrap and no wrap. when the wrap burst bit is set to ?0? the burst read wraps; when it is set to ?1? the burst read does not wrap. burst length bits (cr2-cr0) the burst length bits set the number of words to be output during a synchronous burst read oper- ation as result of a single address latch cycle. they can be set for 4 words, 8 words or continu- ous burst, where all the words are read sequential- ly. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- serts the wait output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 word boundary no wait states are needed and the wait output is not asserted. if the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. wait will be asserted only once during a continuous burst access. see also table 10., burst type definition . cr14, cr5 and cr4 are reserved for future use. table 9. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x-latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 reserved (default) other configurations reserved cr10 wait polarity 0 wait is active low 1 wait is active high (default) cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycle before wait state (default) cr7 burst type 0 interleaved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5-cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 111 continuous (cr7 must be set to ?1?) (default)
m58wr032et, M58WR032EB 28/81 table 10. burst type definition mode start address 4 words 8 words continuous burst sequential interleaved sequential interleaved wrap 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... ... 60 60-61-62-63-64-65-66... 61 61-62-63-wait-64-65-66... 62 62-63-wait-wait-64-65-66... 63 63-wait-wait-wait-64-65- 66... sequential interleaved sequential interleaved no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 same as for wrap (wrap /no wrap has no effect on continuous burst ) 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9... 3 3-4-5-6 3-4-5-6-7-8-9-10 ... 7 7-8-9-10 7-8-9-10-11-12-13-14 ... 60 60-61-62-63 60-61-62-63-64-65-66- 67 61 61-62-63-wait-64 61-62-63-wait-64-65- 66-67-68 62 62-63-wait-wait- 64-65 62-63-wait-wait-64- 65-66-67-68-69 63 63-wait-wait- wait-64-65-66 63-wait-wait-wait- 64-65-66-67-68-69-70
29/81 m58wr032et, M58WR032EB figure 6. x-latency and data output configuration example figure 7. wait configuration example ai08105 a20-a0 valid address k l dq15-dq0 valid data x-latency valid data tacc tavk_cpu tk tqvk_cpu tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle note. settings shown: x-latency = 4, data output held for one clock cycle e tdelay ai08106 a20-a0 valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
m58wr032et, M58WR032EB 30/81 read modes read operations can be performed in two different ways depending on the settings in the configura- tion register. if the clock signal is ?don?t care? for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and data output format are deter- mined by the configuration register. (see config- uration register section for details). all banks supports both asynchronous and synchronous read operations. the multiple bank architecture allows read operations in one bank, while write op- erations are being executed in another (see ta- bles 11 and 12 ). asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corre- sponding to the address latched, that is the mem- ory array, status register, common flash interface or electronic signature depending on the command issued. cr15 in the configuration reg- ister must be set to ?1? for asynchronous opera- tions. in asynchronous read mode a page of data is in- ternally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0 and a1 address inputs. the address inputs a0 and a1 are not gated by latch enable in asyn- chronous read mode. the first read operation within the page has a longer access time (t acc , random access time), subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings apply again. asynchronous read operations can be performed in two different ways, asynchronous random ac- cess read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage so different timings are applied. during asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. in asynchronous read mode, the wait signal is always asserted. see table 20., asynchronous read ac charac- teristics , figure 10., asynchronous random ac- cess read ac waveforms , and figure 11., asynchronous page read ac waveforms , for de- tails. synchronous burst read mode in synchronous burst read mode the data is out- put in bursts synchronized with the clock. it is pos- sible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read opera- tions, such as read status register, read cfi and read electronic signature, single synchro- nous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are con- figured in the configuration register. a burst sequence is started at the first clock edge (rising or falling depending on valid clock edge bit cr6 in the configuration register) after the falling edge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and after a delay of 2 to 5 clock cycles (x latency bits cr13-cr11) the corresponding data are out- put on each clock cycle. the number of words to be output during a syn- chronous burst read operation can be configured as 4 or 8 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output con- figuration bit cr9). the order of the data output can be modified through the burst type and the wrap burst bits in the configuration register. the burst sequence may be configured to be sequential or interleaved (cr7). the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). if the starting address is aligned to the burst length (4 or 8 words), the wrapped configuration has no impact on the output sequence. interleaved mode is not allowed in con- tinuous burst read mode or with no wrap se- quences. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst se- quence; the worst case del ay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. wait is asserted during x latency, the wait state and at the end of 4- and 8-word burst. it is only deasserted when output data are valid. in contin- uous burst read mode a wait state will occur when crossing the first 64 word boundary. if the burst starting address is aligned to a 4 word page, the wait state will not occur. the wait signal can be configured to be active low or active high (default) by setting cr10 in the configuration register. the wait signal is mean- ingful only in synchronous burst read mode, in
31/81 m58wr032et, M58WR032EB other modes, wait is always asserted (except for read array mode). see table 21., synchronous read ac character- istics , and figure 12., synchronous burst read ac waveforms , for details. single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that only the first data output after the x latency is valid. synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is al- ways asserted. see table 21., synchronous read ac character- istics , and figure 13., single synchronous read ac waveforms , for details. dual operations and multiple bank architecture the multiple bank architecture of the m58wr032e provides flex ibility for software de- velopers by allowing code and data to be split with 4mbit granularity. the dual operations feature simplifies the software management of the device and allows code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while pro- gramming or erasing in one bank, read opera- tions are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is re- quired in a bank which is programming or erasing, the program or erase operation can be suspend- ed. also if the suspended operation was erase then a program command can be issued to anoth- er block, so the device can have one block in erase suspend mode, one programming and oth- er banks in read mode. bus read operations are allowed in another bank between setup and con- firm cycles of program or erase operations. the combination of these features means that read op- erations are possible at any moment. tables 11 and 12 show the dual operations possi- ble in other banks and in the same bank. for a complete list of possible commands refer to ap- pendix d., command interface state ta- bles . table 11. dual operations allowed in other banks table 12. dual operations allowed in same bank note: 1. not allowed in the block or word that is being erased or programmed. 2. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program block erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming yes yes yes yes ? ? yes ? erasing yes yes yes yes ? ? yes ? program suspended yes yes yes yes ? ? ? yes erase suspended yes yes yes yes yes ? ? yes status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program block erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming ? (2) yes yes yes ? ? yes ? erasing ? (2) yes yes yes ? ? yes ? program suspended ye s (1) ye s ye s ye s ? ? ? ye s erase suspended ye s (1) ye s ye s ye s ye s (1) ??yes
m58wr032et, M58WR032EB 32/81 block locking the m58wr032e features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows software- only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and lock-down. table 13. , de- fines all of the possible protection states (wp , dq1, dq0), and appendix c. , figure 27. , shows a flowchart for the locking operations. reading a block?s lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subse- quent reads at the address specified in table 6. , will output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when enter- ing lock-down. dq1 indicates the lock-down sta- tus and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software com- mands. an unlocked block can be locked by issu- ing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked- down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down bl ocks can be individual- ly unlocked to the (1,1,0) state by issuing the soft- ware command, where they can be erased and programmed. these blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while wp remains high. when wp is low , blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp was high. device reset or power-down resets all blocks , including those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediatel y, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix d., com- mand interface state tables , for detailed information on which commands are valid during erase suspend.
33/81 m58wr032et, M58WR032EB table 13. lock status note: 1. the lock status is defined by the write protect pin and by dq1 (?1? for a locked-down block) and dq0 (?1? for a locked b lock) as read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. current protection status (1) (wp , dq1, dq0) next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
m58wr032et, M58WR032EB 34/81 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta- ble 14. in the m58wr032e the maximum number of program/ erase cycles depends on the voltage supply used. table 14. program, erase times and program, erase endurance cycles note: 1. t a = ?40 to 85c; v dd = 1.65v to 2.2v; v ddq = 1.65v to 3.3v. 2. the difference between preprogrammed and not preprogrammed is not significant (?30ms). 3. excludes the time needed to execute the command sequence. 4. t.b.a. = to be announced parameter condition min typ typical after 100k w/e cycles max unit v pp = v dd parameter block (4 kword) erase (2) 0.3 1 2.5 s main block (32 kword) erase preprogrammed 0.8 3 4 s not preprogrammed 1.1 4 s bank (4mbit) erase preprogrammed 3 s not preprogrammed 4.5 s parameter block (4 kword) program (3) 40 ms main block (32 kword) program (3) 300 ms word program (3) 10 10 100 s program suspend latency 5 10 s erase suspend latency 5 20 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v pp = v pph parameter block (4 kword) erase 0.3 2.5 s main block (32 kword) erase 0.9 4 s bank (4mbit) erase 3.5 s bank (4mbit) program (quad-enhanced factory program) t.b.a. (4) s 4mbit program quadruple word 510 ms word/ double word/ quadruple word program (3) 8 100 s parameter block (4 kword) program (3) quadruple word 8 ms word 32 ms main block (32 kword) program (3) quadruple word 64 ms word 256 ms program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles
35/81 m58wr032et, M58WR032EB maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 15. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?40 85 c t bias temperature under bias ?40 125 c t stg storage temperature ?65 155 c v io input or output voltage ?0.5 v ddq +0.6 v v dd supply voltage ?0.2 2.45 v v ddq input/output supply voltage ?0.2 3.6 v v pp program voltage ?0.2 14 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m58wr032et, M58WR032EB 36/81 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 16., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 16. operating and ac measurement conditions figure 8. ac measurement i/o waveform figure 9. ac measurement load circuit table 17. capacitance note: sampled only, not 100% tested. m58wr032et, M58WR032EB parameter 70 80 100 units min max min max min max v dd supply voltage 1.7 2.2 1.65 2.2 1.65 2.2 v v ddq supply voltage 1.7 3.3 1.65 3.3 1.65 3.3 v v pp supply voltage (factory environment) 11.4 12.6 11.4 12.6 11.4 12.6 v v pp supply voltage (application environment) -0.4 v ddq +0.4 -0.4 v ddq +0.4 -0.4 v ddq +0.4 v ambient operating temperature ? 40 85 ? 40 85 ? 40 85 c load capacitance (c l ) 30 30 30 pf input rise and fall times 5 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2 ai06162 v ddq c l c l includes jig capacitance 16.7k ? device under test 0.1f v dd 0.1f v ddq 16.7k ? symbol parameter test condition min max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
37/81 m58wr032et, M58WR032EB table 18. dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e = v il , g = v ih 36ma supply current synchronous read (f=40mhz) 4 word 6 13 ma 8 word 8 14 ma continuous 6 10 ma supply current synchronous read (f=54mhz) 4 word 7 16 ma 8 word 10 18 ma continuous 13 25 ma i dd2 supply current (reset) rp = v ss 0.2v 10 50 a i dd3 supply current (standby) e = v dd 0.2v 10 50 a i dd4 supply current (automatic standby) e = v il , g = v ih 10 50 a i dd5 (1) supply current (program) v pp = v pph 815ma v pp = v dd 10 20 ma supply current (erase) v pp = v pph 815ma v pp = v dd 10 20 ma i dd6 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 13 26 ma program/erase in one bank, synchronous read in another bank 16 30 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2v 10 50 a i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
m58wr032et, M58WR032EB 38/81 table 19. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage ?0.5 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1 1.8 1.95 v v pph v pp program voltage factory program, erase 11.4 12 12.6 v v pplk program or erase lockout 0.9 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v
39/81 m58wr032et, M58WR032EB figure 10. asynchronous random access read ac waveforms ai08099 tavav tavqv telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-a20 valid valid l tellh tllqv tlllh tavlh tlhax taxqx wait teltv tehtz note. write enable, w, is high, wait is active low. valid address latch outputs enabled data valid standby tlhgl hi-z hi-z
m58wr032et, M58WR032EB 40/81 figure 11. asynchronous page read ac waveforms ai08100 a2-a20 e g a0-a1 valid address l dq0-dq15 valid address valid address valid address valid address valid data valid data valid data valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait tavav telqv telqx teltv tglqv (1) note 1. wait is active low. valid address latch outputs enabled valid data standby tlhgl hi-z
41/81 m58wr032et, M58WR032EB table 20. asynchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . symbol alt parameter v ddq = 1.65v-2.2v v ddq = 2.2v-3.3v unit 70 80 100 70 80 100 read timings t avav t rc address valid to next address valid min 70 80 100 70 80 100 ns t avqv t acc address valid to output valid (random) max 70 80 100 70 80 100 ns t avqv1 t pag e address valid to output valid (page) max202525252525ns t axqx (1) t oh address transition to output transition min000000ns t eltv chip enable low to wait valid max 14 14 18 20 22 22 ns t elqv (2) t ce chip enable low to output valid max 70 80 100 70 80 100 ns t elqx (1) t lz chip enable low to output transition min000000ns t ehtz chip enable high to wait hi-z max 17 17 20 25 25 25 ns t ehqx (1) t oh chip enable high to output transition min000000ns t ehqz (1) t hz chip enable high to output hi-z max 17 17 20 20 20 20 ns t glqv (2) t oe output enable low to output valid max 20 25 25 30 30 30 ns t glqx (1) t olz output enable low to output transition min000000ns t ghqx (1) t oh output enable high to output transition min000000ns t ghqz (1) t df output enable high to output hi-z max 17 17 20 17 17 20 ns latch timings t av lh t avadv h address valid to latch enable high min 9 9 10 10 10 12 ns t ellh t eladvh chip enable low to latch enable high min101010101012ns t lhax t advhax latch enable high to address transition min9 9109 910ns t lllh t advlad vh latch enable pulse width min 9 9 10 10 10 12 ns t llqv t advlqv latch enable low to output valid (random) max 70 80 100 70 80 100 ns t lhgl t advhgl latch enable high to output enable low min000000ns
m58wr032et, M58WR032EB 42/81 figure 12. synchronous burst read ac waveforms ai08101 dq0-dq15 e g a0-a20 l wait k (4) valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tkhtv tehqx tehqz tghqx tghqz tkhtx hi-z valid note 2 teltv tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. either the falling or the rising edge of the clock can be configured as the active edge. here the active edge if th e rising one. tehel tkhqv tkhqx tkhqv tkhqx hi-z
43/81 m58wr032et, M58WR032EB figure 13. single synchronous read ac waveforms ai08102 dq0-dq15 e g a0-a20 l wait (2) k (4) valid not valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz hi-z not valid note 3 teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. wait is always asserted when addressed bank is in read cfi, read sr or read electronic signature mode. wait signals valid data if the addressed bank is in read array mode. 4. address latched and data output on the rising clock edge. either the falling or the rising edge of the clock can be configured as the active edge. here the active edge if the rising one not valid tglqx tehel tkhtv hi-z
m58wr032et, M58WR032EB 44/81 figure 14. clock input ac waveform table 21. synchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. for other timings please refer to table 20., asynchronous read ac characteristics . symbol alt parameter v ddq = 1.65v-2.2v v ddq = 2.2v-3.3v unit 70 80 100 70 80 100 synchronous read timings t avk h t avcl kh address valid to clock high min 9 9 9 9 9 10 ns t elkh t elclkh chip enable low to clock high min 9 9 9 9 9 10 ns t eltv chip enable low to wait validmax141418202222ns t ehel chip enable pulse width (subsequent synchronous reads) min141414202020ns t ehtz chip enable high to wait hi-zmax141420252525ns t khax t clkhax clock high to address transition min 9 9 10 10 10 10 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max141418202222ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min444555ns t llkh t advlclk h latch enable low to clock high min 9 9 9 10 10 10 ns clock specifications t khkh t clk clock period (f=33mhz) min --- 3030ns clock period (f=40mhz) - - 25 25 - - clock period (f=54mhz) 18.5 18.5 - - - ns t khkl t klkh clock high to clock low clock low to clock high min 4.5 4.5 5 9.5 9.5 9.5 ns t f t r clock fall or rise time max 3 3 3 3 5 5 ns ai06981 tkhkh tf tr tkhkl tklkh
45/81 m58wr032et, M58WR032EB figure 15. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-a20 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai08103 twphwh wp twhgl tqvwpl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhqv twhwpl twhvpl telkv k twhll twhav
m58wr032et, M58WR032EB 46/81 table 22. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. 3. meaningful only if l is always kept low. symbol alt parameter m58wr032e unit 70 80 100 write enable controlled timings t avav t wc address valid to next address valid min 70 80 100 ns t avl h address valid to latch enable high min 9 9 10 ns t avwh (3) t wc address valid to write enable high min 45 50 50 ns t dvwh t ds data valid to write enable high min 45 50 50 ns t ellh chip enable low to latch enable high min 10 10 10 ns t elwl t cs chip enable low to write enable low min 0 0 0 ns t elqv chip enable low to output valid min 70 80 100 ns t elkv chip enable high to clock valid min 9 9 9 ns t ghwl output enable high to write enable low min 17 17 20 ns t lhax latch enable high to address transition min 9 9 10 ns t lllh latch enable pulse width min 9 9 10 ns t whav (3) write enable high to address valid min 0 0 0 ns t whax (3) t ah write enable high to address transition min 0 0 0 ns t whdx t dh write enable high to input transition min 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 ns t whel (2) write enable high to chip enable low min 25 25 25 ns t whgl write enable high to output enable low min 0 0 0 ns t whll write enable high to latch enable low min 0 0 0 ns t whwl t wph write enable high to write enable low min 25 25 25 ns t whqv write enable high to output valid min 95 105 125 ns t wlwh t wp write enable low to write enable high min 45 50 50 ns protection timings t qvvpl output (status register) valid to v pp low min 0 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 0 ns t vphwh t vps v pp high to write enable high min 200 200 200 ns t whvpl write enable high to v pp low min 200 200 200 ns t whwpl write enable high to write protect low min 200 200 200 ns t wphwh write protect high to write enable high min 200 200 200 ns
47/81 m58wr032et, M58WR032EB figure 16. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-a20 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai08104 twpheh wp tehgl tqvwpl twhel bank address valid address l tavlh tlllh tlhax tghel tehwpl tehvpl telkv k tellh twhqv
m58wr032et, M58WR032EB 48/81 table 23. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. symbol alt parameter m58wr032e unit 70 80 100 chip enable controlled timings t avav t wc address valid to next address valid min 70 80 100 ns t av eh t wc address valid to chip enable high min 45 50 50 ns t avlh address valid to latch enable high min 9 9 10 ns t dveh t ds data valid to write enable high min 45 50 50 ns t ehax t ah chip enable high to address transition min 0 0 0 ns t ehdx t dh chip enable high to input transition min 0 0 0 ns t ehel t wph chip enable high to chip enable low min 25 25 25 ns t ehgl chip enable high to output enable low min 0 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 0 ns t elkv chip enable low to clock valid min 9 9 9 ns t eleh t wp chip enable low to chip enable high min 45 50 50 ns t ellh chip enable low to latch enable high min 10 10 10 ns t elqv chip enable low to output valid min 70 80 100 ns t ghel output enable high to chip enable low min 17 17 20 ns t lhax latch enable high to address transition min 9 9 10 ns t lllh latch enable pulse width min 9 9 10 ns t whel (2) write enable high to chip enable low min 25 25 25 ns t whqv write enable high to output valid min 95 105 125 ns t wlel t cs write enable low to chip enable low min 0 0 0 ns protection timings t ehvpl chip enable high to v pp low min 200 200 200 ns t ehwpl chip enable high to write protect low min 200 200 200 ns t qvvpl output (status register) valid to v pp low min000ns t qvwpl output (status register) valid to write protect low min000ns t vpheh t vps v pp high to chip enable high min 200 200 200 ns t wpheh write protect high to chip enable high min 200 200 200 ns
49/81 m58wr032et, M58WR032EB figure 17. reset and power-up ac waveforms table 24. reset and power-up ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 50ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset. symbol parameter test condition 70 80 100 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 10 10 10 s during erase min 20 20 20 s other conditions min 80 80 80 ns t phwl t phel t phgl t phll reset high to write enable low chip enable low output enable low latch enable low min303030ns t plph (1,2) rp pulse width min 50 50 50 ns t vdhph (3) supply voltages high to reset high min505050s ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll
m58wr032et, M58WR032EB 50/81 package mechanical figure 18. vfbga56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, bottom view package outline note: drawing is not to scale. table 25. vfbga56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.000 0.0394 a1 0.200 0.0079 a2 0.660 0.0260 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 7.700 7.600 7.800 0.3031 0.2992 0.3071 d1 5.250 ? ? 0.2067 ? ? ddd 0.080 0.0031 e 0.750 ? ? 0.0295 ? ? e 9.000 8.900 9.100 0.3543 0.3504 0.3583 e1 4.500 ? ? 0.1772 ? ? fd 1.225 ? ? 0.0482 ? ? fe 2.250 ? ? 0.0886 ? ? sd 0.375 ? ? 0.0148 ? ? e1 e d1 d eb a2 a1 a bga-z38 ddd fd fe sd e ball "a1"
51/81 m58wr032et, M58WR032EB figure 19. vfbga56 daisy chain - package connections (top view through package) d c b a 8 7 6 5 4 3 2 1 g f e ai07731
m58wr032et, M58WR032EB 52/81 figure 20. vfbga56 daisy chain - pcb connection proposal (top view through package) d c b a 8 7 6 5 4 3 2 1 g f e ai07755 end point start point
53/81 m58wr032et, M58WR032EB part numbering table 26. ordering information scheme table 27. daisy chain ordering scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m58wr032et 70 zb 6 t device type m58 architecture w = multiple bank, burst mode operating voltage r = v dd = 1.65v to 2.2v, v ddq = 1.65v to 3.3v device function 032et = 32 mbit (x16), top boot 032eb = 32 mbit (x16), bottom boot speed 70 = 70 ns 80 = 80 ns 100 = 100 ns package zb = vfbga56: 7.7x9 mm , 0.75 mm pitch temperature range 6 = ?40 to 85c option t = tape & reel packing example: m58wr032e -zb t device type m58wr032e daisy chain zb = vfbga56: 7.7 x 9mm, 8x7 active ball array , 0.75 mm pitch option t = tape & reel packing
m58wr032et, M58WR032EB 54/81 appendix a. block address tables table 28. top boot block addresses, m58wr032et note: there are two bank regions, region 1 contains all the banks that are made up of main blocks only, region 2 contains the banks that are made up of the parameter and main blocks. bank # size (kword) address range parameter bank 0 4 1ff000-1fffff 1 4 1fe000-1fefff 2 4 1fd000-1fdfff 3 4 1fc000-1fcfff 4 4 1fb000-1fbfff 5 4 1fa000-1fafff 6 4 1f9000-1f9fff 7 4 1f8000-1f8fff 8 32 1f0000-1f7fff 9 32 1e8000-1effff 10 32 1e0000-1e7fff 11 32 1d8000-1dffff 12 32 1d0000-1d7fff 13 32 1c8000-1cffff 14 32 1c0000-1c7fff bank 1 15 32 1b8000-1bffff 16 32 1b0000-1b7fff 17 32 1a8000-1affff 18 32 1a0000-1a7fff 19 32 198000-19ffff 20 32 190000-197fff 21 32 188000-18ffff 22 32 180000-187fff bank 2 23 32 178000-17ffff 24 32 170000-177fff 25 32 168000-16ffff 26 32 160000-167fff 27 32 158000-15ffff 28 32 150000-157fff 29 32 148000-14ffff 30 32 140000-147fff bank 3 31 32 138000-13ffff 32 32 130000-137fff 33 32 128000-12ffff 34 32 120000-127fff 35 32 118000-11ffff 36 32 110000-117fff 37 32 108000-10ffff 38 32 100000-107fff bank 4 39 32 0f8000-0fffff 40 32 0f0000-0f7fff 41 32 0e8000-0effff 42 32 0e0000-0e7fff 43 32 0d8000-0dffff 44 32 0d0000-0d7fff 45 32 0c8000-0cffff 46 32 0c0000-0c7fff bank 5 47 32 0b8000-0bffff 48 32 0b0000-0b7fff 49 32 0a8000-0affff 50 32 0a0000-0a7fff 51 32 098000-09ffff 52 32 090000-097fff 53 32 088000-08ffff 54 32 080000-087fff bank 6 55 32 078000-07ffff 56 32 070000-077fff 57 32 068000-06ffff 58 32 060000-067fff 59 32 058000-05ffff 60 32 050000-057fff 61 32 048000-04ffff 62 32 040000-047fff bank 7 63 32 038000-03ffff 64 32 030000-037fff 65 32 028000-02ffff 66 32 020000-027fff 67 32 018000-01ffff 68 32 010000-017fff 69 32 008000-00ffff 70 32 000000-007fff
55/81 m58wr032et, M58WR032EB table 29. bottom boot block addresses, M58WR032EB note: there are two bank regions, region 1 contains all the banks that are made up of main blocks only, region 2 contains the banks that are made up of the parameter and main blocks. bank # size (kword) address range bank 7 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff bank 6 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff bank 5 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff bank 4 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff bank 3 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff bank 2 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff bank 1 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff parameter bank 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff
m58wr032et, M58WR032EB 56/81 appendix b. common flash interface the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 and 39 show the ad- dresses used to retrieve the data. the query data is always presented on the lowest order data out- puts (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see figure 5., security block and protection register memory map ). this area can be access- ed only in read mode by the final user. it is impos- sible to change the security number after it has been written by st. issue a read array command to return to read mode. table 30. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 31 , 32 , 33 and 34 . query data is always presented on the lowest order data outputs. table 31. cfi query identification string offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 80h security code area lock protection register unique device number and user programmable otp offset sub-section name description value 00h 0020h manufacturer code st 01h 8814h 8815h device code top bottom 02h reserved reserved 03h reserved reserved 04h-0fh reserved reserved 10h 0051h query unique ascii string "qry" "q" 11h 0052h "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table (see table 34. )p = 39h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table na 1ah 0000h
57/81 m58wr032et, M58WR032EB table 32. cfi query system interface information offset data description value 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 millivolts 1.7v 1ch 0022h v dd logic supply maximum program/erase or write voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 millivolts 2.2v 1dh 0017h v pp [programming] supply minimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 millivolts 1.7v 1eh 00c0h v pp [programming] supply maximum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 millivolts 12v 1fh 0004h typical time-out per single byte/word program = 2 n s 16s 20h 0003h typical time-out for quadruple word program = 2 n s 8s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0003h maximum time-out for word program = 2 n times typical 128s 24h 0004h maximum time-out for quadruple word = 2 n times typical 128s 25h 0002h maximum time-out per individual block erase = 2 n times typical 4s 26h 0000h maximum time-out for chip erase = 2 n times typical na
m58wr032et, M58WR032EB 58/81 table 33. device geometry definition offset word mode data description value 27h 0016h device size = 2 n in number of bytes 4 mbytes 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 byte 2ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 m58wr032et 2dh 2eh 003eh 0000h region 1 information number of identical-size erase blocks = 003eh+1 63 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase blocks = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte 35h 38h reserved reserved for future erase block region information na M58WR032EB 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbytes 31h 32h 003eh 0000h region 2 information number of identical-size erase block = 003eh+1 63 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbytes 35h 38h reserved reserved for future erase block region information na
59/81 m58wr032et, M58WR032EB table 34. primary algorithm-specific extended query table offset data description value (p)h = 39h 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h = 3ch 0031h major version number, ascii "1" (p+4)h = 3dh 0030h minor version number, ascii "0" (p+5)h = 3eh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0chip erase supported(1 = yes, 0 = no) bit 1erase suspend supported(1 = yes, 0 = no) bit 2program suspend supported(1 = yes, 0 = no) bit 3legacy lock/unlock supported(1 = yes, 0 = no) bit 4queued erase supported(1 = yes, 0 = no) bit 5instant individual block locking supported(1 = yes, 0 = no) bit 6protection bits supported(1 = yes, 0 = no) bit 7page mode read supported(1 = yes, 0 = no) bit 8synchronous read supported(1 = yes, 0 = no) bit 9simultaneous operation supported(1 = yes, 0 = no) bit 10 to 31reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 40h 0000h (p+8)h = 41h 0000h (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1reserved; undefined bits are ?0? ye s (p+a)h = 43h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0block protect status register lock/unlock bit active(1 = yes, 0 = no) bit 1block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2reserved for future use; undefined bits are ?0? ye s ye s (p+b)h = 44h 0000h (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 1.8v (p+d)h = 46h 00c0h v pp supply optimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12v
m58wr032et, M58WR032EB 60/81 table 35. protection register information table 36. burst read information table 37. bank and erase block region information note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. offset data description value (p+e)h = 47h 0001h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 1 (p+f)h = 48h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 0080h (p+10)h = 49h 0000h (p+11)h = 4ah 0003h 8 bytes (p+12)h= 4bh 0004h 16 bytes offset data description value (p+13)h = 4ch 0003h page-mode read capability bits 0-7?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 8 bytes (p+14)h = 4dh 0003h number of synchronous mode read configuration fields that follow. 3 (p+15)h = 4eh 0001h synchronous mode read capability configuration 1 bit 3-7reserved bit 0-2?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+16)h = 4fh 0002h synchronous mode read capability configuration 2 8 (p+17)h = 50h 0007h synchronous mode read capability configuration 3 cont. m58wr032et (top) M58WR032EB (bottom) description offset data offset data (p+18)h =51h 02h (p+18)h =51h 02h number of bank regions within the device
61/81 m58wr032et, M58WR032EB table 38. bank and erase block region 1 information m58wr032et (top) M58WR032EB (bottom) description offset data offset data (p+19)h =52h 07h (p+19)h =52h 01h number of identical banks within bank region 1 (p+1a)h =53h 00h (p+1a)h =53h 00h (p+1b)h =54h 11h (p+1b)h =54h 11h number of program or erase operations allowed in region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+1c)h =55h 00h (p+1c)h =55h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+1d)h =56h 00h (p+1d)h =56h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+1e)h =57h 01h (p+1e)h =57h 02h types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+1f)h =58h 07h (p+1f)h =58h 07h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+20)h =59h 00h (p+20)h =59h 00h (p+21)h =5ah 00h (p+21)h =5ah 20h (p+22)h =5bh 01h (p+22)h =5bh 00h (p+23)h =5ch 64h (p+23)h =5ch 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+24)h =5dh 00h (p+24)h =5dh 00h (p+25)h =5eh 01h (p+25)h =5eh 01h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved 5eh 01 5eh 01 (p+26)h =5fh 03h (p+26)h =5fh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+27)h =60h 06h bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+28)h =61h 00h (p+29)h =62h 00h (p+2a)h =63h 01h (p+2b)h =64h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+2c)h =65h 00h (p+2d)h =66h 01h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved
m58wr032et, M58WR032EB 62/81 note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. table 39. bank and erase block region 2 information (p+2e)h =67h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved m58wr032et (top) M58WR032EB (bottom) description offset data offset data (p+27)h =60h 01h (p+2f)h =68h 07h number of identical banks within bank region 2 (p+28)h =61h 00h (p+30)h =69h 00h (p+29)h =62h 11h (p+31)h =6ah 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2a)h =63h 00h (p+32)h =6bh 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2b)h =64h 00h (p+33)h =6ch 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2c)h =65h 02h (p+34)h =6dh 01h types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+2d)h =66h 06h (p+35)h =6eh 07h bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+2e)h =67h 00h (p+36)h =6fh 00h (p+2f)h =68h 00h (p+37)h =70h 00h (p+30)h =69h 01h (p+38)h =71h 01h (p+31)h =6ah 64h (p+39)h =72h 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+32)h =6bh 00h (p+3a)h =73h 00h (p+33)h =6ch 01h (p+3b)h =74h 01h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+34)h =6dh 03h (p+3c)h =75h 03h bank region 2 (erase block type 1): page mode and synchronous mode capabilities (defined in table 36. ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved m58wr032et (top) M58WR032EB (bottom) description offset data offset data
63/81 m58wr032et, M58WR032EB note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, region 1 contains all the banks that are made up of main blocks only, region 2 con- tains the banks that are made up of the parameter and main blocks. (p+35)h =6eh 07h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+36)h =6fh 00h (p+37)h =70h 20h (p+38)h =71h 00h (p+39)h =72h 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+3a)h =73h 00h (p+3b)h =74h 01h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+3c)h =75h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in table 36. ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+3d)h =76h (p+3d)h =76h feature space definitions (p+3e)h =77h (p+3e)h =77h reserved m58wr032et (top) M58WR032EB (bottom) description offset data offset data
m58wr032et, M58WR032EB 64/81 appendix c. flowcharts and pseudo codes figure 21. program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
65/81 m58wr032et, M58WR032EB figure 22. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. 4. any address within the bank can equally be used. write 35h ai06171 b start write address 1 & data 1 (3, 4) read status register (4) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (addresstoprogram1, 0x35); /*see note (4)*/ writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (addresstoprogram) ; "see note (4)" /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58wr032et, M58WR032EB 66/81 figure 23. quadruple word program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differing only for bits a0 and a1. 4. any address within the bank can equally be used. write 56h ai06977b start write address 1 & data 1 (3, 4) read status register (4) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (addresstoprogram1, 0x56); /*see note (4) */ writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (addresstoprogram) ; /"see note (4) "/ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
67/81 m58wr032et, M58WR032EB figure 24. program suspend & resume flowchart and pseudo code write 70h ai06173 read status register yes no sr7 = 1 yes no sr2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
m58wr032et, M58WR032EB 68/81 figure 25. block erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can be used also. write 20h (2) ai06174b start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
69/81 m58wr032et, M58WR032EB figure 26. erase suspend & resume flowchart and pseudo code write 70h ai06175 read status register yes no sr7 = 1 yes no sr6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
m58wr032et, M58WR032EB 70/81 figure 27. locking operations flowchart and pseudo code note: 1. any address within the bank can equally be used. write 01h, d0h or 2fh ai06176b read block lock states yes no locking change confirmed? start write 60h (1) locking_operation_command (address, lock_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
71/81 m58wr032et, M58WR032EB figure 28. protection register program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. 3. any address within the bank can equally be used. write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58wr032et, M58WR032EB 72/81 figure 29. enhanced factory program flowchart write 30h address wa1 ai06160 start read status register yes no sr0 = 0? end write d0h address wa1 write pd1 address wa1 write pd2 address wa2 ( 1) yes no read status register write pdn address wan ( 1) yes no read status register read status register no write pd1 address wa1 ( 1) write pdn address wan ( 1) no read status register write ffffh address block wa1 setup phase verify phase sr0 = 0? sr0 = 0? sr0 = 0? sr0 = 0? read status register yes no sr0 = 0? write ffffh address block wa1 sr7 = 0? yes no check sr4, sr3 and sr1 for program, v pp and lock errors exit read status register no write pd2 address wa2 ( 1) sr0 = 0? yes read status register sr7 = 1? check status register for errors yes no yes yes note 1. address can remain starting address wa1 or be incremented. program phase exit phase = / / =
73/81 m58wr032et, M58WR032EB enhanced factory program pseudo code efp_command(addressflow,dataflow,n) /* n is the number of data to be programmed */ { /* setup phase */ writetoflash(addressflow[0],0x30); writetoflash(addressflow[0],0xd0); status_register=readflash(any_address); if (status_register.b7==1){ /*efp aborted for an error*/ if (status_register.b4==1) /*program error*/ error_handler(); if (status_register.b3==1) /*vpp invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } else{ /*program phase*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.b0==1) /*ready for first data*/ for (i=0; i++; i< n){ writetoflash(addressflow[i],dataflow[i]); /* status register polling*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.b0==1); /* ready for a new data */ } writetoflash(another_block_address,ffffh); /* verify phase */ for (i=0; i++; i< n){ writetoflash(addressflow[i],dataflow[i]); /* status register polling*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.b0==1); /* ready for a new data */ } writetoflash(another_block_address,ffffh); /* exit program phase */ /* exit phase */ /* status register polling */ do{ status_register=readflash(any_address); /* e or g must be toggled */ } while (status_register.b7==0); if (status_register.b4==1) /*program failure error*/ error_handler(); if (status_register.b3==1) /*vpp invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } }
m58wr032et, M58WR032EB 74/81 figure 30. quadruple enhanced factory program flowchart note: 1. the address can remain starting address wa1 (in which case the next page is programmed) or can be any address in the sam e block. 2. the address is only checked for the first word of each page as the order to program the words is fixed so that subsequent wor ds in each page can be written to any address. write 75h address wa1 ai08010 start end write pd1 address wa1 ( 1) write pd2 address wa2 ( 2) write pd3 address wa3 ( 2) read status register setup phase program and verify phase sr7 = 0? yes no check sr4, sr3 and sr1 for program, v pp and lock errors exit check sr4 for programming errors yes load phase exit phase write pd4 address wa4 ( 2) sr0 = 0? last page? yes no write ffffh address block wa1 write pd1 address wa1 read status register no first load phase = /
75/81 m58wr032et, M58WR032EB quadruple enhanced factory program pseudo code quad_efp_command(addressflow,dataflow,n) /* n is the number of pages to be programmed.*/ { /* setup phase */ writetoflash(addressflow[0],0x75); for (i=0; i++; i< n){ /*data load phase*/ /*first data*/ writetoflash(addressflow[i],dataflow[i,0]); /*at the first data of the first page, quad-efp may be aborted*/ if (first_page) { status_register=readflash(any_address); if (status_register.sr7==1){ /*efp aborted for an error*/ if (status_register.sr4==1) /*program error*/ error_handler(); if (status_register.sr3==1) /*vpp invalid error*/ error_handler(); if (status_register.sr1==1) /*program to protect block er- ror*/ error_handler(); } } /*2nd data*/ writetoflash(addressflow[i],dataflow[i,1]); /*3rd data*/ writetoflash(addressflow[i],dataflow[i,2]); /*4th data*/ writetoflash(addressflow[i],dataflow[i,3]); /* program&verify phase */ do{ status_register=readflash(any_address); /* e or g must be toggled*/ }while (status_register.sr0==1) } /* exit phase */ writetoflash(another_block_address,ffffh); /* status register polling */ do{ status_register=readflash(any_address); /* e or g must be toggled */ } while (status_register.sr7==0); if (status_register.sr1==1) /*program to protected block error*/ error_handler(); if (status_register.sr3==1) /*vpp invalid error*/ error_handler(); if (status_register.sr4==1) /*program failure error*/ error_handler(); } }
m58wr032et, M58WR032EB 76/81 appendix d. command interface state tables table 40. command interface states - modify table, next state note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, dwp = double word program, qwp = quadruple word program, p/e. c. = program/erase controller. 2. at power-up, all banks are in read array mode. a read array command issued to a busy bank, results in undetermined data out- put. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active, both cycles are ignored. 5. the clear status register command clears the status register error bits except when the p/e.c. is busy or suspended. 6. efp and quad efp are allowed only when status register bit sr0 is set to ?0?.efp and quad efp are busy if block address is first efp address. any other commands are treated as data. current ci state next ci state after command input read array (2) program wp setup (3,4) program dwp, qwp setup (3,4) block erase, bank erase setup (3,4) efp setup quad- efp setup erase confirm p/e resume, block unlock confirm, efp confirm program/ erase suspend read status register clear status register (5) read electronic signature, read cfi query ready ready program setup program setup erase setup efp setup quad-efp setup ready lock/cr setup ready (lock error) ready ready (lock error) otp setup otp busy busy program setup program busy busy program busy program suspended program busy suspend program suspended program busy program suspended erase setup ready (error) erase busy ready (error) busy erase busy erase suspended erase busy suspend erase suspended program in erase suspend erase suspended erase busy erase suspended program in erase suspend setup program in erase suspend busy busy program in erase suspend busy program i n erase suspend suspended program in erase suspend busy suspend program in erase suspend suspended program in erase suspend busy program in erase suspend suspended lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) efp setup ready (error) efp busy ready (error) busy efp busy (6) verify efp verify (6) quad efp setup quad efp busy (6) busy quad efp busy (6)
77/81 m58wr032et, M58WR032EB table 41. command interface states - modify table, next output note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, dwp = double word program, qwp = quadruple word program, p/e. c. = program/erase controller. 2. at power-up, all banks are in read array mode. a read array command issued to a busy bank, results in undetermined data out- put. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active, both cycles are ignored. 5. the clear status register command clears the status register error bits except when the p/e.c. is busy or suspended. 6. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi query mode, depending on the command issued. each bank remains in its last output state until a new command is issued. the next state does not depend on the bank?s output state. current ci state next output state after command input (6) read array (2) program dwp, qwp setup (3,4) block erase, bank erase setup (3,4) efp setup quad- efp setup erase confirm p/e resume, block unlock confirm, efp confirm program/ erase suspend read status register clear status register (5) read electronic signature, read cfi query program setup status register erase setup otp setup program in erase suspend efp setup efp busy efp verify quad efp setup quad efp busy lock/cr setup status register lock/cr setup in erase suspend otp busy array status register output unchanged status register output unchanged status register ready array status register output unchanged status register output unchanged electronic signature/ cfi program busy erase busy program/erase program in erase suspend busy program in erase suspend suspended
m58wr032et, M58WR032EB 78/81 table 42. command interface states - lock table, next state note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, p/e. c. = program/erase controller. 2. efp and quad efp are allowed only when status register bit sr0 is set to ?0?. efp and quad efp are busy if block address is first efp address. any other commands are treated as data. 3. efp and quad efp exit when block address is different from first block address and data is ffffh. 4. if the p/e.c. is active, both cycles are ignored. 5. illegal commands are those not defined in the command set. current ci state next ci state after command input lock/cr setup (4) otp setup (4) block lock confirm block lock-down confirm set cr confirm efp exit, quad efp exit (3) illegal command (5) p/e. c. operation completed ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy n/a busy ready program setup program busy n/a busy program busy ready suspend program suspended n/a erase setup ready (error) n/a busy erase busy ready suspend lock/cr setup in erase suspend erase suspended n/a program in erase suspend setup program in erase suspend busy n/a busy program in erase suspend busy erase suspended suspend program in erase suspend suspended n/a lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) n/a efp setup ready (error) n/a busy efp busy (2) efp verify efp busy (2) n/a verify efp verify (2) ready efp verify (2) ready quadefp setup quad efp busy (2) n/a busy quad efp busy (2) ready quad efp busy (2) ready
79/81 m58wr032et, M58WR032EB table 43. command interface states - lock table, next output note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, p/e. c. = program/erase controller. 2. efp and quad efp exit when block address is different from first block address and data is ffffh. 3. if the p/e.c. is active, both cycles are ignored. 4. illegal commands are those not defined in the command set. current ci state next output state after command input lock/cr setup (3) otp setup (3) block lock confirm block lock-down confirm set cr confirm efp exit, quad efp exit (2) illegal command (4) p/e. c. operation completed program setup status register output unchanged erase setup otp setup program in erase suspend efp setup efp busy efp verify quad efp setup quad efp busy lock/cr setup status register array status register output unchanged lock/cr setup in erase suspend otp busy status register output unchanged array output unchanged output unchanged ready status register output unchanged array output unchanged output unchanged program busy erasebusy program/erase program in erase suspend busy program in erase suspend suspended
m58wr032et, M58WR032EB 80/81 revision history table 44. document revision history date version revision details 07-aug-2002 1.0 first issue 12-dec-2002 1.1 clear status register command , program/erase suspend command , set configuration register command and factory program commands clarified; tables 5 , 7 and 9 modified; erase status bit (sr5) and wait configuration bit (cr8) , clarified; asynchronous read mode , synchronous burst read mode and single synchronous read mode , clarified; wait active low bar removed from figures 10 , 11 . note 4 added to figure 12 and modified in figure 13 . package mechanical information corrected and daisy chain added (figures 19 and 20 ). data at address offsets 35h, 38h is reserved. 07-feb-2003 1.2 85ns speed class removed, 80ns speed class added. 70ns speed class characterized (certain timings modified). block numbering corrected in table 28. , top boot block addresses, m58wr032et . address lines corrected in ac waveforms. 2nd bus write operation address modified for enhanced factory program, setup program, in table 7., factory program commands . clear status register command and program command clarified. data corrected at (p + 37)h = 70h offset in table 39., bank and erase block region 2 information . datasheet promoted from target specification to product preview. 20-may-2003 1.3 automatic standby mode explained under asynchronous read mode . minor text changes in clear status register command , quadruple enhanced factory program command and synchronous burst read mode . bank erase command moved from the standard to the factory program commands. number of bank erase cycles limited to 100. erase replaced by block erase in tables 11 and 12 , dual operations allowed in other banks and the same bank, respectively. i pp2 parameter for v pp = v pph removed from table 18., dc characteristics - currents . v ddq range split into two in tables 20 and 21 , asynchronous and synchronous read ac characteristics: for v ddq = 2.2v to 3.3v, t avqv1 , t eltv , t ehtz , t ehqz , t glqv , t av lh , t ellh and t lllh in table 20 and all the timings in table 21. were modified. 13-apr-2004 2.0 document promoted from product preview to full datasheet status. small text changes.
81/81 m58wr032et, M58WR032EB information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

▲Up To Search▲

Price & Availability of M58WR032EB

	To Download M58WR032EB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .